Sercos IP Core Now on FPGAs and SoCs

I’ve been writing about this topic more than I expected over the past couple of years, as I did not expect the heavy flurry of activity in embedded automation technology that has occurred (see my recent column on this）。我在这个领域的大部分覆盖范围都集中在FPGA和芯片（SOCS）中设计的功能，以使他们能够处理几年前需要多种独立设备的关键自动化任务。

The most recent news on this front comes fromSercos International, the provider of the Sercos automation bus, which announced that it has made theSercos III IP Coreavailable forAltera’s low-cost, low-power Cyclone Vdevices. The IP core can be used on Sercos III master and slave controllers (SERCON100M/S) and includes all hardware functions such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs. According to Sercos International, this move allows Sercos III master and slave devices to be implemented as a single chip solution using either Cyclone V FPGAs or Cyclone V SoCs, which integrate anARM dual-core Cortex-A9 processor.

"The Cyclone V SoC, with its integrated ARM processor, delivers significant performance improvements for computing-intensive applications,” says Christoph Melzer, managing director ofCannon-Automata工业自动化的公关,一个经销商oducts, and supplier of support and services. “For example, complete Sercos master devices can be implemented in the form of a single-chip solution.”

Detailed documentation on the IP core, reference designs and example Ethernet interface diagrams are available from Sercos International.